#ifndef HW_CMPSS_H
#define HW_CMPSS_H

//*************************************************************************************************
//
// The following are defines for the CMPSS register offsets
//
//*************************************************************************************************
#define CMPSS_O_COMPCTL          0x0u  // CMPSS Comparator Control Register
#define CMPSS_O_COMPHYSCTL       0x4u  // CMPSS Comparator Hysteresis Control Register
#define CMPSS_O_COMPSTS          0x8u  // CMPSS Comparator Status Register
#define CMPSS_O_COMPSTSCLR       0xCu  // CMPSS Comparator Status Clear Register
#define CMPSS_O_COMPDACHCTL      0x10u // CMPSS High DAC Control Register
#define CMPSS_O_COMPDACHCTL2     0x14u // CMPSS High DAC Control Register 2
#define CMPSS_O_DACHVALS         0x18u // CMPSS High DAC Value Shadow Register
#define CMPSS_O_DACHVALA         0x1Cu // CMPSS High DAC Value Active Register
#define CMPSS_O_RAMPHREFA        0x20u // CMPSS High Ramp Reference Active Register
#define CMPSS_O_RAMPHREFS        0x24u // CMPSS High Ramp Reference Shadow Register
#define CMPSS_O_RAMPHSTEPVALA    0x28u // CMPSS High Ramp Step Value Active Register
#define CMPSS_O_RAMPHCTLA        0x2Cu // CMPSS High Ramp Control Active Register
#define CMPSS_O_RAMPHSTEPVALS    0x30u // CMPSS High Ramp Step Value Shadow Register
#define CMPSS_O_RAMPHCTLS        0x34u // CMPSS High Ramp Control Shadow Register
#define CMPSS_O_RAMPHSTS         0x38u // CMPSS High Ramp Status Register
#define CMPSS_O_DACLVALS         0x3Cu // CMPSS Low DAC Value Shadow Register
#define CMPSS_O_DACLVALA         0x40u // CMPSS Low DAC Value Active Register
#define CMPSS_O_RAMPHDLYA        0x44u // CMPSS High Ramp Delay Active Register
#define CMPSS_O_RAMPHDLYS        0x48u // CMPSS High Ramp Delay Shadow Register
#define CMPSS_O_CTRIPLFILCTL     0x4Cu // CTRIPL Filter Control Register
#define CMPSS_O_CTRIPLFILCLKCTL  0x50u // CTRIPL Filter Clock Control Register
#define CMPSS_O_CTRIPHFILCTL     0x54u // CTRIPH Filter Control Register
#define CMPSS_O_CTRIPHFILCLKCTL  0x58u // CTRIPH Filter Clock Control Register
#define CMPSS_O_COMPLOCK         0x5Cu // CMPSS Lock Register
#define CMPSS_O_DACHVALS2        0x60u // CMPSS High DAC Value Shadow Register 2
#define CMPSS_O_DACLVALS2        0x64u // CMPSS Low DAC Value Shadow Register 2
#define CMPSS_O_COMPDACLCTL      0x68u // CMPSS Low DAC Control Register
#define CMPSS_O_COMPDACLCTL2     0x6Cu // CMPSS Low DAC Control Register 2
#define CMPSS_O_RAMPLREFA        0x70u // CMPSS Low Ramp Reference Active Register
#define CMPSS_O_RAMPLREFS        0x74u // CMPSS Low Ramp Reference Shadow Register
#define CMPSS_O_RAMPLSTEPVALA    0x78u // CMPSS Low Ramp Step Value Active Register
#define CMPSS_O_RAMPLCTLA        0x7Cu // CMPSS Low Ramp Control Active Register
#define CMPSS_O_RAMPLSTEPVALS    0x80u // CMPSS Low Ramp Step Value Shadow Register
#define CMPSS_O_RAMPLCTLS        0x84u // CMPSS Low Ramp Control Shadow Register
#define CMPSS_O_RAMPLSTS         0x88u // CMPSS Low Ramp Status Register
#define CMPSS_O_RAMPLDLYA        0x8Cu // CMPSS Low Ramp Delay Active Register
#define CMPSS_O_RAMPLDLYS        0x90u // CMPSS Low Ramp Delay Shadow Register
#define CMPSS_O_CTRIPLFILCLKCTL2 0x94u // CTRIPL Filter Clock Control Register 2
#define CMPSS_O_CTRIPHFILCLKCTL2 0x98u // CTRIPH Filter Clock Control Register 2

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPCTL register
//
//*************************************************************************************************
#define CMPSS_COMPCTL_COMPHSOURCE    0x1U // High Comparator Source Select
#define CMPSS_COMPCTL_COMPHINV       0x2U // High Comparator Invert Select
#define CMPSS_COMPCTL_CTRIPHSEL_S    2U
#define CMPSS_COMPCTL_CTRIPHSEL_M    0xCU // High Comparator Trip Select
#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U
#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U  // High Comparator Trip Output Select
#define CMPSS_COMPCTL_ASYNCHEN       0x40U  // High Comparator Asynchronous Path Enable
#define CMPSS_COMPCTL_COMPLSOURCE    0x100U // Low Comparator Source Select
#define CMPSS_COMPCTL_COMPLINV       0x200U // Low Comparator Invert Select
#define CMPSS_COMPCTL_CTRIPLSEL_S    10U
#define CMPSS_COMPCTL_CTRIPLSEL_M    0xC00U // Low Comparator Trip Select
#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U
#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select
#define CMPSS_COMPCTL_ASYNCLEN       0x4000U // Low Comparator Asynchronous Path Enable
#define CMPSS_COMPCTL_COMPDACE       0x8000U // Comparator/DAC Enable

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPHYSCTL register
//
//*************************************************************************************************
#define CMPSS_COMPHYSCTL_COMPHYS_S 0U
#define CMPSS_COMPHYSCTL_COMPHYS_M 0xFU // Comparator Hysteresis Trim

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTS register
//
//*************************************************************************************************
#define CMPSS_COMPSTS_COMPHSTS   0x1U   // High Comparator Status
#define CMPSS_COMPSTS_COMPHLATCH 0x2U   // High Comparator Latched Status
#define CMPSS_COMPSTS_COMPLSTS   0x100U // Low Comparator Status
#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTSCLR register
//
//*************************************************************************************************
#define CMPSS_COMPSTSCLR_HLATCHCLR  0x2U   // High Comparator Latched Status Clear
#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U   // High Comparator EPWMSYNCPER Clear Enable
#define CMPSS_COMPSTSCLR_LLATCHCLR  0x200U // Low Comparator Latched Status Clear
#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACHCTL register
//
//*************************************************************************************************
#define CMPSS_COMPDACHCTL_DACSOURCE     0x1U // DAC Source Control
#define CMPSS_COMPDACHCTL_RAMPSOURCE_S  1U
#define CMPSS_COMPDACHCTL_RAMPSOURCE_M  0x1EU // Ramp Generator Source Control
#define CMPSS_COMPDACHCTL_SELREF        0x20U // DAC Reference Select
#define CMPSS_COMPDACHCTL_RAMPLOADSEL   0x40U // Ramp Load Select
#define CMPSS_COMPDACHCTL_SWLOADSEL     0x80U // Software Load Select
#define CMPSS_COMPDACHCTL_BLANKSOURCE_S 8U
#define CMPSS_COMPDACHCTL_BLANKSOURCE_M 0xF00U  // EPWMBLANK Source Select
#define CMPSS_COMPDACHCTL_BLANKEN       0x1000U // EPWMBLANK Enable
#define CMPSS_COMPDACHCTL_RAMPDIR       0x2000U // Ramp Generator Direction
#define CMPSS_COMPDACHCTL_FREESOFT_S    14U
#define CMPSS_COMPDACHCTL_FREESOFT_M    0xC000U // Free/Soft Emulation Bits

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACHCTL2 register
//
//*************************************************************************************************
#define CMPSS_COMPDACHCTL2_DEENABLE        0x1U // Diode Emulation mode enable
#define CMPSS_COMPDACHCTL2_DEACTIVESEL_S   1U
#define CMPSS_COMPDACHCTL2_DEACTIVESEL_M   0x3EU  // DEACTIVE source select
#define CMPSS_COMPDACHCTL2_BLANKSOURCEUSEL 0x100U // BLANK source upper group select
#define CMPSS_COMPDACHCTL2_RAMPSOURCEUSEL  0x400U // RAMP source upper group select
#define CMPSS_COMPDACHCTL2_XTRIGCFG_S      12U
#define CMPSS_COMPDACHCTL2_XTRIGCFG_M \
    0x3000U // Ramp Generator Cross Trigger
            // Configuration

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALS register
//
//*************************************************************************************************
#define CMPSS_DACHVALS_DACVAL_S 0U
#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALA register
//
//*************************************************************************************************
#define CMPSS_DACHVALA_DACVAL_S 0U
#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPHCTLA register
//
//*************************************************************************************************
#define CMPSS_RAMPHCTLA_RAMPCLKDIV_S 0U
#define CMPSS_RAMPHCTLA_RAMPCLKDIV_M 0x3FFU // Ramp Clock Divider Active Value

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPHCTLS register
//
//*************************************************************************************************
#define CMPSS_RAMPHCTLS_RAMPCLKDIV_S 0U
#define CMPSS_RAMPHCTLS_RAMPCLKDIV_M 0x3FFU // Ramp Clock Divider Shadow Value

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALS register
//
//*************************************************************************************************
#define CMPSS_DACLVALS_DACVAL_S 0U
#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALA register
//
//*************************************************************************************************
#define CMPSS_DACLVALA_DACVAL_S 0U
#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPHDLYA register
//
//*************************************************************************************************
#define CMPSS_RAMPHDLYA_DELAY_S 0U
#define CMPSS_RAMPHDLYA_DELAY_M 0x1FFFU // High Ramp Delay Value Active

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPHDLYS register
//
//*************************************************************************************************
#define CMPSS_RAMPHDLYS_DELAY_S 0U
#define CMPSS_RAMPHDLYS_DELAY_M 0x1FFFU // High Ramp Delay Value Shadow

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPLFILCTL_FILTINSEL_S 0U
#define CMPSS_CTRIPLFILCTL_FILTINSEL_M 0x7U // Filter Input Select
#define CMPSS_CTRIPLFILCTL_SAMPWIN_S   3U
#define CMPSS_CTRIPLFILCTL_SAMPWIN_M   0x1F8U // Sample Window
#define CMPSS_CTRIPLFILCTL_THRESH_S    9U
#define CMPSS_CTRIPLFILCTL_THRESH_M    0x7E00U // Majority Voting Threshold
#define CMPSS_CTRIPLFILCTL_FILINIT     0x8000U // Filter Initialization Bit

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPHFILCTL_FILTINSEL_S 0U
#define CMPSS_CTRIPHFILCTL_FILTINSEL_M 0x7U // Filter Input Select
#define CMPSS_CTRIPHFILCTL_SAMPWIN_S   3U
#define CMPSS_CTRIPHFILCTL_SAMPWIN_M   0x1F8U // Sample Window
#define CMPSS_CTRIPHFILCTL_THRESH_S    9U
#define CMPSS_CTRIPHFILCTL_THRESH_M    0x7E00U // Majority Voting Threshold
#define CMPSS_CTRIPHFILCTL_FILINIT     0x8000U // Filter Initialization Bit

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPLOCK register
//
//*************************************************************************************************
#define CMPSS_COMPLOCK_COMPCTL    0x1U // COMPCTL Lock
#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock
#define CMPSS_COMPLOCK_DACCTL     0x4U // DACCTL Lock
#define CMPSS_COMPLOCK_CTRIP      0x8U // CTRIP Lock

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALS2 register
//
//*************************************************************************************************
#define CMPSS_DACHVALS2_DACVAL_S 0U
#define CMPSS_DACHVALS2_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALS2 register
//
//*************************************************************************************************
#define CMPSS_DACLVALS2_DACVAL_S 0U
#define CMPSS_DACLVALS2_DACVAL_M 0xFFFU // DAC Value Control

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACLCTL register
//
//*************************************************************************************************
#define CMPSS_COMPDACLCTL_DACSOURCE     0x1U // DAC Source Control
#define CMPSS_COMPDACLCTL_RAMPSOURCE_S  1U
#define CMPSS_COMPDACLCTL_RAMPSOURCE_M  0x1EU // Ramp Generator Source Control
#define CMPSS_COMPDACLCTL_RAMPLOADSEL   0x40U // Ramp Load Select
#define CMPSS_COMPDACLCTL_BLANKSOURCE_S 8U
#define CMPSS_COMPDACLCTL_BLANKSOURCE_M 0xF00U  // EPWMBLANK Source Select
#define CMPSS_COMPDACLCTL_BLANKEN       0x1000U // EPWMBLANK Enable
#define CMPSS_COMPDACLCTL_RAMPDIR       0x2000U // Ramp Generator Direction

//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACLCTL2 register
//
//*************************************************************************************************
#define CMPSS_COMPDACLCTL2_BLANKSOURCEUSEL 0x100U // BLANK source upper group select
#define CMPSS_COMPDACLCTL2_RAMPSOURCEUSEL  0x400U // RAMP source upper group select

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPLCTLA register
//
//*************************************************************************************************
#define CMPSS_RAMPLCTLA_RAMPCLKDIV_S 0U
#define CMPSS_RAMPLCTLA_RAMPCLKDIV_M 0x3FFU // Ramp Clock Divider Active Value

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPLCTLS register
//
//*************************************************************************************************
#define CMPSS_RAMPLCTLS_RAMPCLKDIV_S 0U
#define CMPSS_RAMPLCTLS_RAMPCLKDIV_M 0x3FFU // Ramp Clock Divider Shadow Value

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPLDLYA register
//
//*************************************************************************************************
#define CMPSS_RAMPLDLYA_DELAY_S 0U
#define CMPSS_RAMPLDLYA_DELAY_M 0x1FFFU // Low Ramp Delay Value Active

//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPLDLYS register
//
//*************************************************************************************************
#define CMPSS_RAMPLDLYS_DELAY_S 0U
#define CMPSS_RAMPLDLYS_DELAY_M 0x1FFFU // Low Ramp Delay Value Shadow

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCLKCTL2 register
//
//*************************************************************************************************
#define CMPSS_CTRIPLFILCLKCTL2_CLKPRESCALEU_S 0U
#define CMPSS_CTRIPLFILCLKCTL2_CLKPRESCALEU_M 0xFFU // Sample Clock Prescale Upper Bits

//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCLKCTL2 register
//
//*************************************************************************************************
#define CMPSS_CTRIPHFILCLKCTL2_CLKPRESCALEU_S 0U
#define CMPSS_CTRIPHFILCLKCTL2_CLKPRESCALEU_M 0xFFU // Sample Clock Prescale Upper Bits

#endif
